The present invention relates to a semiconductor device having a multi-level interconnect structure, and more particularly, it relates to a semiconductor device including a dummy pattern useful in planarization of an interlayer insulating film formed on an interconnect pattern and a method for fabricating the same.
Recently, in accordance with improvement in integration and performance of semiconductor devices, interconnect patterns included in a device are refined and formed in multiple levels. Owing to the refinement and the multi-level structure of the interconnect patterns, a level difference caused on the top face of an interlayer insulating film has become large and abrupt, which degrades the processing accuracy and the reliability of the interconnect patterns.
In particular, a difference in the height (absolute height) between the top face of a wafer and the top face of an interlayer insulating film, namely, the so-called global level difference, is increased due to the multi-level structure of metal interconnects. Furthermore, since exposing light of a shorter wavelength is employed in the lithography as the device is more refined, the depth of focus becomes insufficient. As a result, the processing accuracy and the reliability of the interconnect patterns are degraded. As a planarization technique for an interlayer insulating film for reducing the global level difference, chemical mechanical polishing (CMP) is employed.
Furthermore, the refinement and the multi-level structure of the interconnect patterns in accordance with the increase in integration level of semiconductor devices can increase capacitance between interconnects. The increase of the capacitance between interconnects affects the operation speed of the semiconductor device, and hence, the capacitance between interconnects needs to be reduced. In order to reduce the capacitance between interconnects, an insulating material with a low dielectric constant is used, and in order to further reduce the capacitance between interconnects, an air gap interconnect structure where air gaps are provided between interconnect patterns are employed.
The air gap interconnect structure is reported in, for example, papers written by T. Ueda et al. (A Novel Air Gap Integration Scheme for Multi-level Interconnects using Self-aligned Via Plugs: 1988 Symposium on VLSI Technology Digest of Technical Papers, P. 46, 1998; and Integration of 3 Level Air Gap Interconnect for Sub-quarter Micron CMOS: 1999 Symposium on VLSI Technology Digest of Technical Papers, P. 111, 1999).
Also in the formation of air gap multi-level interconnects, it is necessary to planarize an interlayer insulating film. In the planarization by the CMP, a dummy pattern is disposed in a portion where interconnect patterns are relatively sparse.
A conventional semiconductor device having the an air gap interconnect structure including a dummy pattern used for the planarization of an interlayer insulating film will now be described with reference to accompanying drawings.
FIGS. 7A through 7C and 8A through 8C are cross-sectional views for showing procedures in a method for fabricating the conventional semiconductor device including an air gap interconnect pattern and a dummy pattern.
First, as shown in FIG. 7A, a first insulating film 102 of silicon oxide, a conducting film 103 of aluminum alloy and a second insulating film 104 of silicon oxide are successively deposited on a semiconductor substrate 101 of silicon. Subsequently, a contact hole 104a for exposing the conducting film 103 is selectively formed in the second insulating film 104.
Next, as shown in FIG. 7B, the contact hole 104a is filled with tungsten, thereby forming a plug 105.
Then, as shown in FIG. 7C, the second insulating film 104 is etched back so as to expose an upper portion of the plug 105. The position of the top of an air gap subsequently formed in the interconnect pattern is determined by controlling the thickness of the second insulating film 104 remaining after the etch back.
Subsequently, as shown in FIG. 8A, a resist pattern 121A for a first interconnect pattern and a resist pattern 121B for a dummy pattern are formed on the second insulating film 104. With the resist patterns 121A and 121B and the plug 105 used as a mask, the second insulating film 104, the conducting film 103 and the first insulating film 102 are successively etched, thereby forming, from the conducting film 103, a first interconnect pattern 103a and a dummy pattern 103b having a square plane shape. At this point, a portion of the first insulating film 102 sandwiched between patterns of the first interconnect pattern 103a is trenched by the etching. Accordingly, an air gap can be easily formed from a space between the patterns and the position of the air gap from the substrate surface can be adjusted.
Next, as shown in FIG. 8B, after removing the resist patterns 121A and 121B, a third insulating film 107 of silicon oxide with low coverage and high directivity is deposited on the entire surface of the semiconductor substrate 101. Thereafter, a fourth insulating film 108 of silicon oxide with high coverage is formed. At this point, an air gap 122 is formed between the patterns of the first interconnect pattern 103a. Thus, the air gap interconnect structure is obtained.
Then, as shown in FIG. 8C, the top face of the fourth insulating film 108 is polished and planarized by the CMP until the top face of the plug 105 is exposed.
In the fabrication method for the conventional semiconductor device, however, although the dummy pattern 103b is formed in a region where the first interconnect pattern 103a is relatively sparse on the semiconductor substrate 101, a difference h1 in the absolute height of the top face of the fourth insulating film 108 between a portion above the first interconnect pattern 103a and a portion above the dummy pattern 103b cannot be sufficiently small as shown in FIG. 8B. Therefore, even though the fourth insulating film 108 is planarized, there remains a difference h2 in the absolute height as shown in FIG. 8C. Thus, a sufficiently planar face cannot be attained.
When a second interconnect pattern is formed on the fourth insulating film 108 with such a difference h2 remaining, interconnects included in the second interconnect pattern may be disconnected due to the difference h2 or may fail due to high resistance. In order to more sufficiently planarize the top face of the fourth insulating film 108, a larger number of dummy patterns 103b may be provided. When a larger number of dummy patterns 103b are provided, however, capacitance between interconnect layers and between interconnects become so large that it is difficult to attain high operation speed. Therefore, the number of dummy patterns 103b is not preferably increased.